The present invention relates to semiconductor devices, and relates particularly, but not exclusively, to DRAM memory devices using SOI (silicon on insulator) technology.
DRAM memories are known in which each memory cell consists of a single transistor and a single capacitor, the binary 1's and 0's of data stored in the DRAM being represented by the capacitor of each cell being in a charged or discharged state. Charging and discharging of the capacitors is controlled by switching of the corresponding transistor, which also controls reading of the data stored in the cell. Such an arrangement is disclosed in U.S. Pat. No. 3,387,286 and will be familiar to persons skilled in the art.
Semiconductor devices incorporating MOSFET (metal oxide semiconductor field effect transistor) type devices are well known, and arrangements employing SOI (silicon on insulator) are becoming increasingly available. SOI technology involves the provision of a silicon substrate carrying an insulating silicon dioxide layer coated with a layer of silicon in which the individual field effect transistors are formed by forming source and drain regions of doped silicon of one polarity separated by a body of doped silicon of the opposite polarity.
SOI technology suffers the drawback that because the body region of each individual transistor is electrically insulated from the underlying silicon substrate, electrical charging of the body can occur under certain conditions. This can have an effect on the electrical performance of the transistors and is generally regarded as an undesirable effect. Extensive measures are generally taken to avoid the occurrence of this effect, as described in more detail in a “Suppression of parasitic bipolar action in ultra thin film fully depleted CMOS/simox devices by Ar-ion implantation into source/drain regions”, published by Terukazu Ohno et al. in IEEE Transactions on Electron Devices, Vol. 45, Number 5 May 1998.
A known DRAM device is also described in U.S. Pat. No. 4,298,962, in which the DRAM is formed from a plurality of cells, each of which consists of an IGFET (insulated gate field effect transistor) formed directly on a silicon substrate. This DRAM enables the injection of charge carriers from a semiconductor impurity region of opposite polarity to the polarity of the source and drain regions and which is located in the source or drain, or the injection of charge carriers from the silicon substrate.
This known device suffers from the drawback that it requires at least four terminal connections for its operation (connected to the drain, gate, source and impurity region of opposite polarity or to the substrate), which increases the complexity of the device. Furthermore, the memory function of each cell is ensured only while voltages are being applied to the transistor source and drain, which affects the reliability of the device, and writing, reading and refreshing of the stored information must be performed in so-called “punch through” mode, which results in heavy power consumption by the device.
An attempt to manufacture DRAM memories using SOI technology is disclosed in U.S. Pat. No. 5,448,513. In that known device, each memory cell is formed from two transistors, one of which is used for writing data to the memory cell, and one of which is used for reading data stored in the device. As a result of each cell consisting of two separate transistors, each cell requires four terminal connections for its operation, which increases the complexity of the device, as well as the surface area necessary for each memory cell as a result of the provision of two transistors.
Preferred embodiments of the present invention seek to overcome the above disadvantages of the prior art.